1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT18HTF12872FD - 1GB MT18HTF25672FD - 2GB Features Figure 1: 240-Pin FBDIMM (MO-256 R/C B) * 240-pin, DDR2 fully buffered dual in-line memory module (FBDIMM) * Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400 * 1GB (128 Meg x 72), 2GB (256 Meg x 72) * 3.2 Gb/s, 4 Gb/s, or 4.8 Gb/s link transfer rates * High-speed, 1.5V differential, point-to-point link between the host controller and advanced memory buffer (AMB) * Fault-tolerant; can work around a bad bit lane in each direction * High-density scaling with up to eight FBDIMM devicess per channel * SMBus interface to AMB for configuration register access * In-band and out-of-band command access * Deterministic protocol Module height: 30.35mm (1.19in) * * * * * * * * * * * * Options * Package - 240-pin DIMM (Pb-free) * Frequency/CAS latency - 2.5ns @ CL = 5 (DDR2-800) - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533)1 Note: Marking Y -80E -667 -53E 1. Not recommended for new designs. - Enables memory controller to optimize DRAM accesses for maximum performance - Delivers precise control and repeatable memory behavior Automatic DDR2 SDRAM bus and channel calibration Transmitter de-emphasis to reduce ISI MBIST and IBIST test functions Transparent mode for DRAM test support VDD = VDDQ = 1.8V for DRAM VREF = 0.9V SDRAM command/address termination VCC = 1.5V for AMB VDDSPD = 3-3.6V for AMB and EEPROM Serial presence-detect (SPD) with EEPROM Gold edge contacts Dual rank Supports 95C operation with 2X refresh PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 CL = 3 -80E PC2-6400 800 533 - 12.5 12.5 55 -667 PC2-5300 667 533 400 15 15 55 -53E PC2-4200 - 533 400 15 15 55 tRCD (ns) tRP tRC (ns) (ns) Table 2: Addressing Parameter 1GB Refresh count 8K 8K 4 BA[1:0] 8 BA[2:0] 1KB 1KB 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) Device bank address Device page size per bank Device configuration 2GB Row address 16K A[13:0] 16K A[13:0] Column address 2K A[9:0] 2K A[9:0] Module rank address 2 S#[1:0] 2 S#[1:0] Table 3: Part Numbers and Timing Parameters - 1GB Base device: MT47H64M8,1 512Mb DDR2 SDRAM Module Part Number2 Density Configuration Module Memory Clock/ Clock Cycles Link Transfer Bandwidth Data Rate (CL-tRCD-tRP) Rate MT18HTF12872FDY-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s MT18HTF12872FDY-667__ 1GB 128 Meg x 72 MT18HTF12872FDY-53E__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s Table 4: Part Numbers and Timing Parameters - 2GB Base device: MT47H128M8,1 1Gb DDR2 SDRAM Module Part Number2 Density Configuration Module Memory Clock/ Clock Cycles Link Transfer Bandwidth Data Rate (CL-tRCD-tRP) Rate MT18HTF25672FDY-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s MT18HTF25672FDY-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s MT18HTF25672FDY-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s Notes: 1. Data sheets for the base devices can be found on Micron's Web page. 2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revisions. Consult factory for current revision codes. Example: MT18HTF25672FDY-667E1D4. PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 240-Pin FBDIMM Front 240-Pin FBDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VDD 31 PN3 61 2 VDD 32 PN3# 3 VDD 33 VSS 4 VSS 34 5 VDD 35 6 VDD 36 VSS 7 VDD 37 PN5 8 VSS 38 Pin Symbol Pin Symbol Pin Symbol VDD 151 SN3 181 SS9#1 Pin Symbol PS9#1 121 PN9# 91 SN9# 211 62 VSS 92 VSS 122 VDD 152 SN3# 63 PN10 93 PS5 123 VDD 153 VSS 182 VSS 212 VSS 183 SN10 213 SS5 PN4 64 PN10# 94 PS5# 124 VSS 154 PN4# 65 VSS 95 VSS 125 VDD 155 SN4 184 SN10# 214 SS5# SN4# 185 VSS 215 VSS 66 PN11 96 PS6 126 VDD 156 VSS 67 PN11# 97 PS6# 127 VDD 157 SN5 186 SN11 216 SS6 187 SN11# 217 SS6# PN5# 68 VSS 98 VSS 128 VSS 158 SN5# 188 VSS 218 VSS 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 10 VCC 40 PN131 70 PS0 100 PS7# 130 VCC 160 SN131 190 SS0 220 SS7# 11 VSS 41 PN13#1 71 PS0# 101 VSS 131 VSS 161 SN13#1 191 SS0# 221 VSS 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 SS8# 14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS 15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU 16 DNU 46 VSS 76 PS2 106 DNU 136 DNU 166 VSS 196 SS2 226 DNU 17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_Test (DNU) 167 VSS 197 SS2# 227 VSS 18 VSS 48 PN121 78 VSS 108 VDD 138 VSS 168 SN121 198 VSS 228 SCK PN12#1 79 PS3 109 VDD 139 DNU 169 SN12#1 199 SS3 229 SCK# 19 DNU 49 20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD 23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 VSS 235 VDD 26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 DNU 236 VDD 27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 DNU 237 VTT 28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD 29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0 30 VSS 60 PN9 90 PS91 120 SCL 150 VSS 180 SN9 210 SS91 240 SA1 Note: PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, SS9/SS9#. 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock Input, negative line. SCL Input Serial presence-detect (SPD) clock input. SS[9:0] Input Secondary southbound data, positive lines. SS#[9:0] Input Secondary southbound data, negative lines. PN[13:0] Output Primary northbound data, positive lines. PN#[13:0] Output Primary northbound data, negative lines. SN[13:0] Output Secondary northbound data, positive lines. SN#[13:0] Output Secondary northbound data, negative lines. SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB. SDA I/O SPD data input/output. RESET# Supply AMB reset signal. VCC Supply AMB core power and AMB channel interface power (1.5V). VDD Supply DRAM power and AMB DRAM I/O power (1.8V). VDDSPD Supply SPD/AMB SMBUS power (3.3V). VSS Supply Ground. VTT Supply DRAM address/command/clock termination power (VDD/2). M_Test - The M_Test pin provides an external connection for testing the margin of VREF, which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and will be included in this specification at that time. DNU - Do not use. PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM System Block Diagram System Block Diagram Figure 2: System Block Diagram DDR2 connector with unique key 10 Memory controller 14 SMBus Commodity DDR2 SDRAM devices DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component AMB AMB AMB DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component Up to 8 modules * * * DDR2 component DDR2 component AMB CK source SMBus access to buffer registers Common clock source PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Functional Block Diagram Functional Block Diagram Figure 3: Functional Block Diagram CS1# CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U1 DQS DQS# U19 DQS1 DQS1# DM5 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U18 DQS DQS# DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U6 DQS DQS# U13 U2 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U12 DQS DQS# U7 DQS6 DQS6# DM6 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U3 DQS DQS# DM/ RDQS U17 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS3# DM5 DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U8 DQS DQS# U11 DQS7 DQS7# DM7 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS U16 DQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# PN[13:0] Out to controller PN#[13:0] In from controller PS[9:0] PS#[9:0] Data input/output signals to DDR2 channel U1-U4, U6-U9, U10-U19 DQ[63:0] U4 A M B DQS#[8:0] CB[7:0] DM[8:0] Command, address, and clock signals to DDR2 channel U1-U4, U6-U9, U10-U19 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VTT Clock, command, and address line terminations: SCK, SCK# CK0, CK0#, CK1, CK1#, ODT0, CS0#, CKE0, RAS#, CAS#, WE#, A[15:0], BA[2:0] RESET# U20 A1 Out to adjacent FBDIMM VDDSPD SA0 SA[2:] SPD EEPROM A[15:0] RAS#, CAS# WE#, ODT0 CS0#, CS1# CKE0, CKE1 In from adjacent FBDIMM CK0, CK0# CK1, CK1# SCL SDA CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ U10 DQS DQS# U9 DQS8 DQS8# DM8 SN[13:0] SN#[13:0] SS[9:0] SS#[9:0] DQS[8:0] DM/ RDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U5 VTT SDA 6 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS U14 DQS# DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# U15 Terminators SPD EEPROM, AMB VCC AMB VDD DDR2 SDRAM VREF DDR2 SDRAM VSS A2 VSS SA0 SA1 SA2 PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN DM/ RDQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2# DM2 WP A0 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DQS5# DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SCL DM/ RDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DDR2 SDRAM SPD EEPROM, AMB Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM General Description General Description Micron's FBDIMM devices adhere to the currently proposed industry specifications for FBDIMMs. The following specifications contain detailed information on FBDIMM design, interfaces, and theory of operation and are listed here for the system designers' convenience. Refer to the JEDEC Web site for available specifications. * * * * * FBDIMM Design Specification - pending JEDEC approval FBDIMM: Architecture and Protocol - JESD206 FBDIMM: Advanced Memory Buffer (AMB) - JESD82-20 Design for Test, Design for Validation (DFx) Specification Serial Presence-Detect (SPD) for Fully Buffered DIMM - JEDEC Standard No. 21-C, page 4.1.2.7-1 This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from the channel behind an AMB buffer on the FBDIMM. Memory device capacity remains high, and total memory capacity scales with DDR2 SDRAM bit density. As shown in the System Block Diagram, the FBDIMM channel provides a communication path from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM devices from the channel enhances the communication path and significantly increases the reliability and availability of the memory subsystem. Advanced Memory Buffer The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB component, located in the center of each FBDIMM, acts as a repeater and buffer for all signals and commands exchanged between the host controller and DDR2 SDRAM devices, including data input and output. The AMB communicates with the host controller and adjacent FBDIMMs on a system board using an industry-standard, high-speed, differential, 1.5V, point-to-point interface. The AMB also enables buffering of memory traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification for further information. IDD Conditions and Specifications Table 7: IDD Conditions Symbol Condition IDD_IDLE_0 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IDLE_1 Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_ACTIVE_1 Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH IDD_ACTIVE_2 Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM IDD Conditions and Specifications Table 7: IDD Conditions (Continued) Symbol Condition IDD_TRAINING Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IBIST IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_EI Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW Note: 1. Actual test conditions may vary from published JEDEC test conditions. Table 8: IDD Specifications - 1GB DDR2-533 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2200 3000 3400 3200 3500 3800 2000 A IDD 1420 1420 2545 1420 1420 1420 326 A 6.2 7.4 10.2 7.7 8.2 8.7 3.8 W Total power Table 9: IDD Specifications - 1GB DDR2-667 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2600 3400 3900 3700 4000 4500 2500 A IDD 1510 1510 2777 1510 1510 1510 326 A 7.0 8.2 11.4 8.7 9.2 10.0 4.6 W Total power Table 10: IDD Specifications - 1GB DDR2-800 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC TBD TBD TBD TBD TBD TBD TBD A IDD TBD TBD TBD TBD TBD TBD TBD A Total power TBD TBD TBD TBD TBD TBD TBD W Table 11: IDD Specifications - 2GB DDR2-533 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2200 3000 3400 3200 3500 3800 2000 A IDD 1420 1420 2425 1420 1420 1420 326 A 6.2 7.4 10.0 7.7 8.2 8.7 3.8 W Total power PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 12: IDD Specifications - 2GB DDR2-667 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2600 3400 3900 3700 4000 4500 2500 A IDD 1420 1420 2515 1420 1420 1420 326 A 6.8 8.1 11.0 8.5 9.0 9.8 4.6 W Total power Table 13: IDD Specifications - 12B DDR2-800 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC TBD TBD TBD TBD TBD TBD TBD A IDD TBD TBD TBD TBD TBD TBD TBD A Total power TBD TBD TBD TBD TBD TBD TBD W Note: 1. Total power is based on maximum voltage levels, ICC at 1.575V and IDD at 1.9V. Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3 3.6 V Input high voltage: Logic 1; all inputs VIH VDDSPD x 0.7 VDDSPD + 0.5 V Input low voltage: Logic 0; all inputs VIL -0.6 VDDSPD x 0.3 V Output low voltage: IOUT = 3mA EEPROM and AMB supply voltage VOL - 0.4 V Input leakage current: VIN = GND to VDD ILI 0.10 3 A Output leakage current: VOUT = GND to VDD ILO 0.05 3 A Standby current ISB 1.6 4 A Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA Table 15: Serial Presence-Detect EEPROM AC Operating Conditions Symbol Min Max Units Notes SCL LOW to SDA data-out valid Parameter/Condition tAA 0.2 0.9 s 1 Time the bus must be free before a new transition can start tBUF 1.3 - s Data-out hold time tDH 200 - ns tF - 300 ns Data-in hold time tHD:DAT 0 - s Start condition hold time tHD:STA 0.6 - s tHIGH SDA and SCL fall time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 9 0.6 - s tI - 50 ns tLOW 1.3 - s 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 15: Serial Presence-Detect EEPROM AC Operating Conditions (Continued) Parameter/Condition Symbol Min Max Units Notes tR - 0.3 s 2 fSCL - 400 kHz Data-in setup time tSU:DAT 100 - ns Start condition setup time tSU:STA 0.6 - s Stop condition setup time tSU:STO 0.6 - s tWRC - 10 ms SDA and SCL rise time SCL clock frequency WRITE cycle time Notes: 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pullup resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/ SPD. PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions Module Dimensions Figure 4: 240-Pin DDR2 FBDIMM Front view 5.1 (0.201) MAX 133.50 (5.256) 133.20 (5.244) 66.68 (2.63) TYP 0.595 (0.0234) R 0.75 (0.03) R 8X 0.5 (0.02) R (4X) 2.0 (0.079) TYP 1.5 (0.059) R (4X) U1 U2 U4 U3 U5 17.3 (0.681) TYP 9.5 (0.374) TYP 2.6 (0.102) D (2X) 5.2 (0.205) TYP 1.25 (0.0492) TYP Pin 1 Detail A 1.0 (0.039) TYP 0.75 (0.03) R Pin 120 123.0 (4.843) TYP 9.9 (0.39) TYP (x4) 1.37 (0.054) 1.17 (0.046) 3.9 (0.153) TYP (x2) 0.8 (0.031) TYP 74.68 (2.94) TYP 5.48 (0.216) TYP 30.5 (1.201) 30.2 (1.189) 45 x 0.18 (0.0071) Back view 1.06 (0.042) 1.19 (0.047) 1.06 (0.042) Detail A 3.1 (0.122) TYP U6 U7 U8 U10 24.95 (0.982) TYP U11 U9 3.05 (0.12) TYP 2.18 (0.086) TYP 120 (2X) Pin 240 5.0 (0.197) TYP 51.0 (2.01) TYP Pin 121 67.0 (2.638) TYP 66.68 (2.63) TYP 7.68 (0.302) MAX* Front view with heat spreader U1 U2 U4 U3 U5 1.37 (0.054) 1.17 (0.046) Back view with heat spreader U6 U7 U8 U10 *Including clip radius 7.92 (0.312) U11 U9 Notes: PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef81a2f237 htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2005 Micron Technology, Inc. All rights reserved.